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Test Engineer

Company: ATR International
Location: Milpitas
Posted on: August 2, 2022

Job Description:

We are seeking a Lead Design For Test (DFT) Engineer for a very important client.
The company is an innovative enterprise that designs, develops and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage and other dynamic technologies that drive today's leading-edge applications. The company combines world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, the company is headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities.
The company is seeking a Lead Design For Test (DFT) Engineer for the R&D team based out of our Santa Clara, CA Office. This position is a hands-on technical position, working closely with the customer, design, and implementation teams. Primary Responsibilities: - Support and work closely with automotive customers (with special emphasis on in-system test using LBIST & MBIST) and non-automotive customers in defining the ASIC DFT requirements and specifications - Development and Implementation of DFT Architecture - Design and Verification of DFT logic and components - Generation of structural test vectors, analysis and coverage improvement - Generation of timing constraints for the various DFT modes - Work with design and implementation teams on DFT STA, logical, physical and power issues - Support ATE team with test vector porting, diagnosis and physical failure analysis
The ideal candidate will possess the following qualifications:
Necessary Qualifications: - BS/MS in Electrical Engineering, Computer Science or related field - Minimum of 15 years hands-on work experience in ASIC DFT design. Experience in an SoC product development organization or in an ASIC vendor company along with customer facing experience preferable - Strong working knowledge of Chip design, Verilog/System Verilog and design verification - Expertise and knowledge about DFT methodologies, industrial standards and practices - Hands-on experience with DFT circuit insertion and validation for scan, at-speed, MBIST and Boundary scan. - Experience with DFT/ATPG EDA tools like Tessent/TestMax/Modus. Experience with simulators and waveform debug tools. - Experience with STA tools like Primetime, SDF generation and Gate-level simulations - Understanding and expert handling of Verilog HDL based Netlists, design libraries and Scripting (Perl/Tcl/)

Keywords: ATR International, Milpitas , Test Engineer, Engineering , Milpitas, California

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