Forward Error Correction (FEC) SoC Design Engineer
Posted on: January 20, 2023
Oversees definition, design, verification, and documentation of
state-of-the-art Forward Error Correction (FEC) and Ethernet
physical layer IP for next generation FPGA families. Analyzes
complex FEC algorithms and develops parameterizable and efficient
IP implementations, for both ASIC and FPGA. Defines and develops
future FEC cores. Determines microarchitecture design, logic
design, RTL coding, and system simulation. Performs all aspects of
the design flow from high level design to synthesis. Oversees
physical design place and route, and timing and power model
generation. Participates in planning and execution of design
verification and silicon validation. If you have strong
Reed-Solomon background, and a passion for cutting-edge FEC
development, the Intel Programmable Solutions Group would love to
speak with you.
QualificationsBachelor's Degree in Engineering or related
field.M.Sc.; Ph.D. in relevant subject area strongly preferred.
3+ years of experience with:
High-speed forward error correction (FEC) blocks, especially
Reed-Solomon codecs; the ideal candidate will also have a strong
theoretical background in this area.
1+ years of experience with the following:
Hardware design experience in RTL, preferably on large, complex
Digital design flows including RTL simulation, timing
Familiarity with ASIC design flows (libraries, EDA tools,
verification methods, etc.).
Broad FEC background (Viterbi, LPDC, etc.).
Working understanding of IEEE Ethernet standards.
-Requirements listed would be obtained through a combination of
industry relevant job experience, internship experiences and/or
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the
acquisition of Altera. As part of Intel, PSG will create
market-leading programmable logic devices that deliver a wider
range of capabilities than customers experience today. Combining
Altera's industry-leading FPGA technology and customer support with
Intel's world-class semiconductor manufacturing capabilities will
enable customers to create the next generation of electronic
systems with unmatched performance and power efficiency. PSG takes
pride in creating an energetic and dynamic work environment that is
driven by ingenuity and innovation. We believe the growth and
success of our group is directly linked to the growth and
satisfaction of our employees. That is why PSG is committed to a
work environment that is flexible and collaborative, and allows our
employees to reach their full potential.
Intel strongly encourages employees to be vaccinated against
COVID-19. Intel aligns to federal, state, and local laws and as a
contractor to the U.S. Government is subject to government mandates
that may be issued. Intel policies for COVID-19 including guidance
about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment
without regard to race, color, religion, religious creed, sex,
national origin, ancestry, age, physical or mental disability,
medical condition, genetic information, military and veteran
status, marital status, pregnancy, gender, gender expression,
gender identity, sexual orientation, or any other characteristic
protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in
the industry. It consists of competitive pay, stock, bonuses, as
well as, benefit programs which include health, retirement, and
vacation. Find more information about all of our Amazing Benefits
Annual Salary Range for jobs which could be performed in US,
*Salary range dependent on a number of factors including location
This role will be eligible for our hybrid work model which allows
employees to split their time between working on-site at their
assigned Intel site and off-site. In certain circumstances the work
model may change to accommodate business needs.
Keywords: INTEL, Milpitas , Forward Error Correction (FEC) SoC Design Engineer, Engineering , Milpitas, California
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